Afleveringen
-
In Part 2 of the special FutureCast 2026 holiday series, Harry Foster continues exploring how the semiconductor landscape is rapidly changing — and why the next phase of innovation will be shaped as much by constraints as by breakthroughs.
This episode examines the forces pushing systems toward specialization, the growing challenge of data movement, and the rising impact of power, security, and runtime behavior on system correctness. Harry also discusses how verification teams can scale as complexity expands and why agentic AI will become essential to automation and workflow orchestration.
Key Discussion Points:
Why specialization becomes unavoidable as AI, robotics, and domain-specific compute accelerate
The growing impact of data movement bottlenecks and memory-centric architectures
How HBM, near-memory compute, analog accelerators, and photonics break legacy abstractions
Why physical effects such as thermals and statistical variation now influence functional correctness
How verification evolves across cross-domain workflows without overwhelming engineering teams
The role of hybrid digital twins in unifying logic, performance, physical behavior, and verification intent
Why power ceilings, security boundaries, and model drift become architectural concerns
How runtime safety, isolation, and lifecycle monitoring reshape verification planning
Why agentic AI shifts from tool enhancement to workflow orchestration and continuous validation
Predictions for 2026: AI-assisted verification becomes standard, and data movement emerges as a verification challenge
Predictions for 2030: thermal- and statistical-aware verification become standard practice, and agentic AI drives verification infrastructure while curated chiplet marketplaces begin to form -
Join host Harry Foster for a special holiday edition of Bugged Out. In this first episode of the two-part FutureCast 2026 series, Harry steps away from the usual guest interviews to look at how the semiconductor industry is evolving — and why innovation is now happening far above the transistor.
This episode explores why modern silicon behaves less like a static product and more like a living, continuously changing system. Harry highlights the technologies driving this shift, from multi-die architectures to software-defined hardware, and explains how verification must expand across the entire product lifecycle.
Key discussion points:
Why innovation has moved above the transistor
How chiplets, hybrid bonding, and HBM are redefining system
performance
The collapse of traditional design boundaries across logic,
timing, thermals, and software
Emerging system-level behaviors in multi-die architectures
Why these changes reshape verification across physical and logical domains
The role of hybrid digital twins in capturing system truth
How software-defined products evolve after shipping
Why OTA updates become verification events
The shift from traditional to lifecycle-aware verification
Predictions for 2026: multi-die verification becomes essential, and lifecycle-aware verification becomes mandatory for advanced AI-driven devices
Predictions for 2030: hybrid digital twins become foundational, and early chiplet vendors enter the market with curated offerings -
Zijn er afleveringen die ontbreken?
-
Episode Title: Better Stimulus Generation Through AI: Shaping the Future of Functional Verification
Host: Harry Foster
Guest: Tom Fitzpatrick, Industry Expert and Major Contributor to the Verification Academy
Episode Summary
Join host Harry Foster on Bugged Out as he welcomes industry veteran Tom Fitzpatrick to explore the transformative power of AI in functional verification. In this episode, Tom, author of the whitepaper "Better Stimulus Generation Through AI," delves into how Questa One Portable Stimulus Assist is revolutionizing stimulus generation. He compares traditional UVM approaches with the Portable Test and Stimulus Standard (PSS), discusses the evolving skill sets for engineers in an AI-driven world, and shares his vision for the future of verification. Tune in to understand why PSS is set to become the next major leap in productivity and abstraction for chip verification!
Key Discussion Points:
The Mission of Bugged Out: Harry introduces the podcast's goal: to bring candid conversations about finding and fixing bugs in complex chips.
Meet the Expert: Jake Wiltgen, an expert in safety-critical systems, functional safety standards, and DFT, shares his extensive industry experience.
What is DFT? Jake breaks down Design for Test in an accessible way, explaining its primary objective: to deliver high-quality, functionally correct silicon by building in capabilities to test for manufacturing defects.
Jake's Journey into DFT: Discover how Jake got pulled into the world of DFT, driven by growing needs for fault-grading and addressing long-running serial simulations.
Tackling the Tapeout Bottleneck: Learn why DFT sign-off often becomes a bottleneck during the critical period between netlist drop and tapeout, and how Questa One helps accelerate these essential simulations.
Mega-Trends in DFT: Harry and Jake discuss the impact of technology scaling, design scaling, and system scaling on engineers, noting that the growing volume of DFT verification at both block and top levels is a major challenge.
Evolving Challenges: Reliability and Aging Silicon: Explore how the objectives of DFT remain the same, but the methods have evolved dramatically due to embedded AI, autonomous vehicles, and angstrom-scale technology nodes.
In-System Test (IST) in Practice: Jake paints a vivid picture of IST, illustrating its benefits in data centers (predicting silicon failure) and automotive (detecting safety-critical system failures before they cause harm).
Resources Mentioned:
White Paper: "Better Stimulus Generation Through AI" by Tom Fitzpatrick. -
Episode Title: Accelerating DFT Sign-off: Getting the Bugs Out of Complex Chips
Host: Harry Foster
Guest: Jake Wiltgen, Director of IC Verification Solutions at Siemens EDA
________________________________________
Episode Summary
Join host Harry Foster on Bugged Out as he dives deep into the world of functional verification with special guest Jake Wiltgen from Siemens EDA.
This episode explores the critical role of Design for Test (DFT) in ensuring high-quality silicon for today's most complex chips. Jake shares his journey into DFT, explains why it's more crucial than ever, and highlights key insights from his whitepaper, "Accelerating DFT sign-off with Questa One."
Discover how new verification technologies are tackling bottlenecks, addressing mega-trends in chip design, and evolving to meet the challenges of silicon reliability and in-system test.
________________________________________
Key Discussion Points
The Mission of Bugged Out: Harry introduces the podcast's goal: to bring candid conversations about finding and fixing bugs in complex chips.
Meet the Expert: Jake Wiltgen, an expert in safety-critical systems, functional safety standards, and DFT, shares his extensive industry experience.
What is DFT? Jake breaks down Design for Test in an accessible way, explaining its primary objective: to deliver high-quality, functionally correct silicon by building in capabilities to test for manufacturing defects.
Jake's Journey into DFT: Discover how Jake got pulled into the world of DFT, driven by growing needs for fault-grading and addressing long-running serial simulations.
Tackling the Tapeout Bottleneck: Learn why DFT sign-off often becomes a bottleneck during the critical period between netlist drop and tapeout, and how Questa One helps accelerate these essential simulations.
Mega-Trends in DFT: Harry and Jake discuss the impact of technology scaling, design scaling, and system scaling on engineers, noting that the growing volume of DFT verification at both block and top levels is a major challenge.
Evolving Challenges: Reliability and Aging Silicon: Explore how the objectives of DFT remain the same, but the methods have evolved dramatically due to embedded AI, autonomous vehicles, and angstrom-scale technology nodes.
In-System Test (IST) in Practice: Jake paints a vivid picture of IST, illustrating its benefits in data centers (predicting silicon failure) and automotive (detecting safety-critical system failures before they cause harm).
________________________________________
Resources Mentioned
White Paper: "Accelerating DFT sign-off with Questa One" by Jake Wiltgen.
